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1 of 14 070900 features real time clock counts seconds, minutes hours, date of the month, month, day of the week, and year with leap year compensation valid up to 2100 31 x 8 ram for scratchpad data storage serial i/o for minimum pin count 2.0?5.5v full operation uses less than 300 na at 2.0v single?byte or multiple?byte (burst mode) data transfer for read or write of clock or ram data 8?pin dip or optional 8?pin soics for surface mount simple 3?wire interface ttl?compatible (v cc = 5v) optional industrial temperature range ?40c to +85c ds1202 compatible recognized by underwriters laboratory ordering information part # description ds1302 8?pin dip ds1302n 8-pin dip (industrial) ds1302s 8?pin soic (200 mil) ds1302sn 8?pin soic (industrial) ds1302z 8?pin soic (150 mil) ds1302zn 8?pin soic (industrial) ds1302s-16 16-pin soic (300 mil) DS1302SN-16 16-pin soic (industrial) pin assignment pin description x1, x2 ? 32.768 khz crystal pins gnd ? ground rst ? reset i/o ? data input/output sclk ? serial clock v cc1 , v cc2 ? power supply pins description the ds1302 trickle charge timekeeping chip contains a real time clock/calendar and 31 bytes of static ram. it communicates with a microprocessor via a simple serial interface. the real time clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the end of the month date is automatically adjusted for months with less than 31 days, including corrections for leap year. the clock operates in either the 24?hour or 12?hour format with an am/pm indicator ds1302 v cc2 x1 x2 gnd v cc1 sclk i/o rst 8 7 6 5 1 2 3 4 ds1302 8-pin dip (300 mil) v cc2 x1 x2 gnd v cc1 sclk i/o rst 8 7 6 5 1 2 3 4 ds1302s 8-pin soic (200 mil) ds1302z 8-pin soic (150 mil) 16-pin soic v cc1 nc sc l k nc i/ o nc nc nc rst v cc2 nc x1 nc x2 nc gnd 1 2 3 4 5 6 8 7 1 6 15 14 1 3 12 11 9 10 tiger electronic co.,ltd
ds1302 2 of 14 interfacing the ds1302 with a microprocessor is simplified by using synchronous serial communication. only three wires are required to communicate with the clock/ram: (1) rst (reset), (2) i/o (data line), and (3) sclk (serial clock). data can be transferred to and from the clock/ram 1 byte at a time or in a burst of up to 31 bytes. the ds1302 is designed to operate on very low power and retain data and clock information on less than 1 microwatt. the ds1302 is the successor to the ds1202. in addition to the basic timekeeping functions of the ds1202, the ds1302 has the additional features of dual power pins for primary and back?up power supplies, programmable trickle charger for v cc1 , and seven additional bytes of scratchpad memory. operation the main elements of the serial timekeeper are shown in figure 1: shift register, control logic, oscillator, real time clock, and ram. ds1302 block diagram figure 1 signal descriptions v cc1 ? v cc1 provides low power operation in single supply and battery operated systems as well as low power battery backup. in systems using the trickle charger, the rechargeable energy source is connected to this pin. v cc2 ? vcc2 is the primary power supply pin in a dual supply configuration. v cc1 is connected to a backup source to maintain the time and date in the absence of primary power. the ds1302 will operate from the larger of v cc1 or v cc2 . when v cc2 is greater than v cc1 + 0.2v, v cc2 will power the ds1302. when v cc2 is less than v cc1 , v cc1 will power the ds1302. sclk (serial clock input) ? sclk is used to synchronize data movement on the serial interface. i/o (data input/output) ? the i/o pin is the bi-directional data pin for the 3-wire interface. rst (reset) ? the reset signal must be asserted high during a read or a write.
ds1302 3 of 14 x1, x2 ? connections for a standard 32.768 khz quartz crystal. the internal oscillator is designed for operation with a crystal having a specified load capacitance of 6 pf. for more information on crystal selection and crystal layout considerations, please consult application note 58, ?crystal considerations with real time clocks.? the ds1302 can also be driven by an external 32.768 khz oscillator. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is floated. command byte the command byte is shown in figure 2. each data transfer is initiated by a command byte. the msb (bit 7) must be a logic 1. if it is 0, writes to the ds1302 will be disabled. bit 6 specifies clock/calendar data if logic 0 or ram data if logic 1. bits 1 through 5 specify the designated registers to be input or output, and the lsb (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. the command byte is always input starting with the lsb (bit 0). address/command byte figure 2 reset and clock control all data transfers are initiated by driving the rst input high. the rst input serves two functions. first, rst turns on the control logic which allows access to the shift register for the address/command sequence. second, the rst signal provides a method of terminating either single byte or multiple byte data transfer. a clock cycle is a sequence of a falling edge followed by a rising edge. for data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. if the rst input is low all data transfer terminates and the i/o pin goes to a high impedance state. data transfer is illustrated in figure 3. at power?up, rst must be a logic 0 until v cc > 2.0 volts. also sclk must be at a logic 0 when rst is driven to a logic 1 state. data input following the eight sclk cycles that input a write command byte, a data byte is input on the rising edge of the next eight sclk cycles. additional sclk cycles are ignored should they inadvertently occur. data is input starting with bit 0. data output following the eight sclk cycles that input a read command byte, a data byte is output on the falling edge of the next eight sclk cycles. note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. additional sclk cycles retransmit the data bytes should they inadvertently occur so long as rst remains high. this operation permits continuous burst mode read capability. also, the i/o pin is tri?stated upon each rising edge of sclk. data is output starting with bit 0. burst mode burst mode may be specified for either the clock/calendar or the ram registers by addressing location 31 decimal (address/command bits 1 through 5 = logic 1). as before, bit 6 specifies clock or ram and bit 0
ds1302 4 of 14 specifies read or write. there is no data storage capacity at locations 9 through 31 in the clock/calendar registers or location 31 in the ram registers. reads or writes in burst mode start with bit 0 of address 0. when writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. however, when writing to ram in burst mode it is not necessary to write all 31 bytes for the data to transfer. each byte that is written to will be transferred to ram regardless of whether all 31 bytes are written or not. clock/calendar the clock/calendar is contained in seven write/read registers as shown in figure 4. data contained in the clock/ calendar registers is in binary coded decimal format (bcd). clock halt flag bit 7 of the seconds register is defined as the clock halt flag. when this bit is set to logic 1, the clock oscillator is stopped and the ds1302 is placed into a low?power standby mode with a current drain of less than 100 nanoamps. when this bit is written to logic 0, the clock will start. the initial power on state is not defined. am-pm/12-24 mode bit 7 of the hours register is defined as the 12? or 24?hour mode select bit. when high, the 12?hour mode is selected. in the 12?hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24?hour mode, bit 5 is the second 10-hour bit (20 ? 23 hours). write protect bit bit 7 of the control register is the write-protect bit. the first seven bits (bits 0 ? 6) are forced to 0 and will always read a 0 when read. before any write operation to the clock or ram, bit 7 must be 0. when high, the write protect bit prevents a write operation to any other register. the initial power on state is not defined. therefore the wp bit should be cleared before attempting to write to the device. trickle charge register this register controls the trickle charge characteristics of the ds1302. the simplified schematic of figure 5 shows the basic components of the trickle charger. the trickle charge select (tcs) bits (bits 4 -7) control the selection of the trickle charger. in order to prevent accidental enabling, only a pattern of 1010 will enable the trickle charger. all other patterns will disable the trickle charger. the ds1302 powers up with the trickle charger disabled. the diode select (ds) bits (bits 2 ? 3) select whether one diode or two diodes are connected between v cc2 and v cc1 . if ds is 01, one diode is selected or if ds is 10, two diodes are selected. if ds is 00 or 11, the trickle charger is disabled independently of tcs. the rs bits (bits 0 -1) select the resistor that is connected between v cc2 and v cc1 . the resistor selected by the resistor select (rs) bits is as follows: rs bits resistor typical value 00 none none 01 r1 2 k ? 10 r2 4 k ? 11 r3 8 k ? if rs is 00, the trickle charger is disabled independently of tcs.
ds1302 5 of 14 diode and resistor selection is determined by the user according to the maximum current desired for battery or super cap charging. the maximum charging current can be calculated as illustrated in the following example. assume that a system power supply of 5 volt is applied to v cc2 and a super cap is connected to v cc1 . also assume that the trickle charger has been enabled with one diode and resistor r1 between v cc2 and v cc1 . the maximum current i max would therefore be calculated as follows: i max = (5.0v ? diode drop) / r1 ~ (5.0v ? 0.7v) / 2 k ? ~ 2.2 ma obviously, as the super cap charges, the voltage drop between v cc2 and v cc1 will decrease and therefore the charge current will decrease. clock/calendar burst mode the clock/calendar command byte specifies burst mode operation. in this mode the first eight clock/calendar registers can be consecutively read or written (see figure 4) starting with bit 0 of address 0. if the write protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to any of the eight clock/calendar registers (this includes the control register). the trickle charger is not accessible in burst mode. at the beginning of a clock burst read, the current time is transferred to a second set of registers. the time information is read from these secondary registers, while the clock may continue to run. this eliminates the need to re-read the registers in case of an update of the main registers during a read. ram the static ram is 31 x 8 bytes addressed consecutively in the ram address space. ram burst mode the ram command byte specifies burst mode operation. in this mode, the 31 ram registers can be consecutively read or written (see figure 4) starting with bit 0 of address 0. register summary a register data format summary is shown in figure 4. crystal selection a 32.768 khz crystal can be directly connected to the ds1302 via x1 and x2. the crystal selected for use should have a specified load capacitance (cl) of 6 pf. for more information on crystal selection and crystal layout consideration, please consult application note 58, ?crystal considerations with real time clocks."
ds1302 6 of 14 data transfer summary figure 3 single byte read single byte write in burst mode, rst is kept high and additional sclk cycles are sent until the end of the burst. rst sclk i/o r/ w a0 a1 a2 a3 a4 r/c 1 r/ w a0 a1 a2 a3 a4 r/c 1 rst sclk i/o d0 d1 d2 d3 d4 d5 d6 d7
ds1302 7 of 14 register address/definition figure 4
ds1302 8 of 14 ds1302 programmable trickle charger figure 5
ds1302 9 of 14 absolute maximum ratings* voltage on any pin relative to ground ?0.5v to +7.0v operating temperature 0c to 70c or - 40 c to +85 c for industrial storage temperature ?55c to +125c soldering temperature 260c for 10 seconds (dip) see ipc/jedec standard j-std-020a for surface mount devices * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 o c to 70 o c or -40 parameter symbol min typ max units notes supply voltage v cc1 , v cc2 v cc1, v cc2 2.0 5.5 v 1, 11 logic 1 input v ih 2.0 v cc +0.3 v 1 v cc =2.0v -0.3 +0.3 logic 0 input v il v cc =5v ?0.3 +0.8 v1 *-40c to +85c for industrial device. dc electrical characteristics (0 o c to 70 o c or -40 parameter symbol min typ max units notes input leakage i li +500 a6 i/o leakage i lo +500 a6 v cc =2.0v 1.6 logic 1 output v oh v cc =5v 2.4 v2 v cc =2.0v 0.4 logic 0 output v ol v cc =5v 0.4 v3 v cc1 =2.0v 0.4 active supply current i cc1a v cc1 =5v 1.2 ma 5, 12 v cc1 =2.0v 0.3 timekeeping current i cc1t v cc1 =5v 1 a 4, 12 v cc1 =2.0v 100 v cc1 =5v 100 standby current i cc1s ind 200 na 10, 12, 14 v cc2 =2.0v 0.425 active supply current i cc2a v cc2 =5v 1.28 ma 5, 13 v cc2 =2.0v 25.3 timekeeping current i cc2t v cc2 =5v 81 a 4, 13 v cc2 =2.0v 25 standby current i cc2s v cc2 =5v 80 a 10, 13 trickle charge resistors r1 r2 r3 2 4 8 k ? k ? k ? trickle charge diode voltage drop v td 0.7 v *unless otherwise noted.
ds1302 10 of 14 capacitance (t a = 25 o c) parameter symbol min typ max units notes input capacitance c i 10 pf i/o capacitance c i/o 15 pf crystal capacitance c x 6pf ac electrical characteristics (0 o c to 70 o c or -40 parameter symbol min typ max units notes v cc =2.0v 200 data to clk setup t dc v cc =5v 50 ns 7 v cc =2.0v 280 clk to data hold t cdh v cc =5v 70 ns 7 v cc =2.0v 800 clk to data delay t cdd v cc =5v 200 ns 7, 8, 9 v cc =2.0v 1000 clk low time t cl v cc =5v 250 ns 7 v cc =2.0v 1000 clk high time t ch v cc =5v 250 ns 7 v cc =2.0v 0.5 clk frequency t clk v cc =5v dc 2.0 mhz 7 v cc =2.0v 2000 clk rise and fall t r , t f v cc =5v 500 ns v cc =2.0v 4 rst to clk setup t cc v cc =5v 1 s 7 v cc =2.0v 240 clk to rst hold t cch v cc =5v 60 ns 7 v cc =2.0v 4 rst inactive time t cwh v cc =5v 1 s 7 v cc =2.0v 280 rst to i/o high z t cdz v cc =5v 70 ns 7 v cc =2.0v 280 sclk to i/o high z t ccz v cc =5v 70 ns 7 *unless otherwise noted.
ds1302 11 of 14 timing diagram: read data transfer figure 5 timing diagram: write data transfer figure 6 notes: 1. all voltages are referenced to ground. 2. logic one voltages are specified at a source current of 1 ma at v cc =5v and 0.4 ma at v cc =2.0v, v oh =v cc for capacitive loads. 3. logic zero voltages are specified at a sink current of 4 ma at v cc =5v and 1.5 ma at v cc =2.0v, v ol =gnd for capacitive loads. 4. i cc1t and i cc2t are specified with i/o open, rst set to a logic ?0?, and clock halt flag=0 (oscillator enabled). 5. i cc1a and i cc2a are specified with the i/o pin open, rst high, sclk=2 mhz at v cc =5v; sclk=500 khz, v cc =2.0v and clock halt flag=0 (oscillator enabled). 6. rst , sclk, and i/o all have 40 k ? pull?down resistors to ground. 7. measured at v ih =2.0v or v il =0.8v and 10 ns maximum rise and fall time. 8. measured at v oh =2.4v or v ol =0.4v. 9. load capacitance = 50 pf. 10. i cc1s and i cc2s are specified with rst , i/o, and sclk open. the clock halt flag must be set to logic one (oscillator disabled). 11. v cc =v cc2 , when v cc2 >v cc1 +0.2v; v cc =v cc1 , when v cc1 >v cc2 . 12. v cc2 =0v. 13. v cc1 =0v. 14. typical values are at 25c.
ds1302 12 of 14 ds1302 serial timekeeper 8?pin dip (300-mil) pkg 8-pin dim min max a in. mm 0.360 9.14 0.400 10.16 b in. mm 0.240 6.10 0.260 6.60 c in. mm 0.120 3.05 0.140 3.56 d in. mm 0.300 7.62 0.325 8.26 e in. mm 0.015 0.38 0.040 1.02 f in. mm 0.120 3.04 0.140 3.56 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.320 8.13 0.370 9.40 j in. mm 0.008 0.20 0.012 0.30 k in. mm 0.015 0.38 0.021 0.53
ds1302 13 of 14 ds1302s serial timekeeper 8?pin soic (150-mil and 200-mil) pkg 8-pin (150 mil) 8-pin (200 mil) dim min max min max a in. mm 0.188 4.78 0.196 4.98 0.203 5.16 0.213 5.41 b in. mm 0.150 3.81 0.158 4.01 0.203 5.16 0.213 5.41 c in. mm 0.048 1.22 0.062 1.57 0.070 1.78 0.074 1.88 e in. mm 0.004 0.10 0.010 0.25 0.004 0.10 0.010 0.25 f in. mm 0.053 1.35 0.069 1.75 0.074 1.88 0.084 2.13 g in. mm 0.050 bsc 1.27 bsc h in. mm 0.230 5.84 0.244 6.20 0.302 7.67 0.318 8.08 j in. mm 0.007 0.18 0.011 0.28 0.006 0.15 0.010 0.25 k in. mm 0.012 0.30 0.020 0.51 0.013 0.33 0.020 0.51 l in. mm 0.016 0.41 0.050 1.27 0.019 0.48 0.030 0.76 phi 0
ds1302 14 of 14 ds1302s serial timekeeper 16-pin soic pkg 16-pin dim min max ain mm 0.398 10.11 0.412 10.46 bin mm 0.290 7.37 0.300 7.62 cin mm 0.089 2.26 0.095 2.41 ein mm 0.004 0.102 0.012 0.30 fin mm 0.004 2.39 0.105 2.67 gin mm 0.050 bsc 1.27 bsc hin mm 0.398 10.11 0.416 10.57 jin mm 0.009 0.229 0.013 0.33 kin mm 0.013 0.33 0.020 0.51 lin mm 0.016 0.40 0.040 1.02 phi 0 8

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